1. Field of the Invention
The present disclosure relates generally to a semiconductor fabrication and, more particularly, to a non-volatile memory device having sidewall floating gates which can control two bits with just one transistor.
2. Background of the Related Art
In general, there are two categories in a semiconductor device, namely, a volatile memory and a non-volatile memory. The volatile memory is again divided into a dynamic random access memory (hereinafter referred to as “DRAM”) and a static DRAM (hereinafter referred to as “SDRAM”). One characteristic of the volatile memory is that data are maintained just while power is being applied. In other words, when power is cut, the data in the volatile memory disappear. On the other hand, the non-volatile memory, mainly a ROM (Read Only Memory), can keep the data regardless of power being applied thereto.
From the point of a view of the fabrication process, the non-volatile memory is divided into a floating gate type and a metal insulator semiconductor (hereinafter referred to as “MIS”) type. The MIS type has doubly or triply deposited dielectric layers which comprise at least two kinds of dielectric materials.
The floating gate type implements the memorizing characteristic using potential wells and, recently, an ETOX (Electrically erasable programmable read only memory Tunnel OXide) used in a flash EEPROM (Electrically Erasable Programmable Read Only Memory) is a well-known structure.
Alternatively, the MIS type performs the program/erase operation using traps at dielectric layer bulk, interface between dielectric layers, and interface between dielectric layer and a semiconductor. A metal/silicon ONO Semiconductor (hereinafter referred to as “MONOS/SONOS”) structure mainly used to the flash EEPROM is a representative structure.
A Conventional SONOS memory device comprises a tunnel oxide layer, a trap nitride layer and a block oxide layer on a P-type silicon substrate, and a gate deposited thereon.
In the SONOS memory device, a program operation is performed by FN-tunneling or directly tunneling electrons so that the electrons are trapped at a predetermined site in the trap nitride layer, thereby increasing a threshold voltage. An erase operation moves the electrons by various tunneling ways such as the FN-tunneling, the direct tunneling, and a trap assisted tunneling so that the electrons are withdrawn from the P-type silicon substrate, thereby decreasing the threshold voltage.
Because the conventional SONOS device has employed the tunneling method for the program/erases operation as described above, the thickness of the tunnel oxide has to be at most about 20 Å to achieve adequate program/erase operating speed. However, the thinness of the tunnel oxide (e.g., 20 Å) may detrimentally affect the retention characteristic of the memory device. Thus, various methods have been provided to solve such a problem in the SONOS device. One known method is to thicken the tunnel oxide layer and employ a thermal electron injection to perform the program operation and a hot hole injection to conduct the erase operation, thereby improving the retention characteristic. However, the above-described method radically deteriorates the endurance characteristic of the SONOS device.
FIG. 1 is a cross-sectional view illustrating a floating gate of a conventional single bit stack gate type.
Referring to FIG. 1, a tunneling oxide layer comprising an SiO2 layer 14 is formed on a P-type silicon substrate 11. A polysilicon floating gate 15 is formed on the tunneling oxide layer of the resulting structure. An oxide-nitride-oxide (hereinafter referred to as “ONO”) layer 16 is formed to increase the coupling ratio. A control gate 17 is formed on the ONO layer 16. A source 13 and drain 12 are then made adjacent to each side of bottom of the SiO2 layer 14.
FIG. 2 represents a graph illustrating the distribution of the threshold voltage of the program/erase operation of the floating gate of a conventional single bit stack gate type.
Referring to FIG. 2, the threshold voltage of a cell 18 can become under 0[V] by an over-erase during the erase operation. In that case, the threshold distribution of the erase operation is higher than that of the program operation to thereby decrease a threshold window. In other words, only one over-erased cell in the bit line may induct excessive current into the bit line and, therefore, interrupt to read data of other cells along the bit line. Such the over-erase may be caused by various structural problems such as a critical dimension in the cell of the flash memory, the thickness of the tunneling oxide layer, a junction overlap, the critical dimension of the floating gate, uniformity of the floating gate, the thickness of the ONO layer, the damage of the tunneling oxide layer, and pin holes. A well-known conventional method for solving the over-erase problem comprises steps of: detecting over-erased cell; and reprogramming the detected over-erased cell in order to increase the threshold voltage thereof.
However, the step of detecting the over-erased cell is a time-consuming job and, additionally, complicated circuits are required to recover the detected over-erased cell. Moreover, the threshold voltage distribution during the erase operation is high and affects the threshold voltage distribution of a later program operation. Consequently, the threshold window voltage decreases and a multi-level bit is hardly achieved in accordance with the conventional art methods.